A router comprises a device that routes one or more signals appearing at the router input(s) to one or more outputs. Routers used in the broadcast industry typically employ at least a first router portion with a plurality of router modules (also referred to as matrix cards) coupled to at least one expansion module. The expansion module couples the first router chassis to one or more second router portion to allow further routing of signals. Many broadcast routers, and especially those that are linearly expandable, route asynchronous signals. Asynchronous signal routing by such linearly expandable routers requires an accurate clock signal throughout the entire route to preserve the integrity of routed data. For an asynchronous signal, a difference in clock frequency from one location to another can cause corruption of the signal and loss of the data represented by that signal. Even a difference in clock frequencies as small as 1 part per million (PPM) can have an undesirable effect on data. Typical examples of data corruption include repeated or dropped signal samples.
As linearly expandable routers increase in complexity, the problem of supplying an accurate and synchronized clock signal to various elements becomes more difficult. For purposes of discussion, a clock signal constitutes a signal that oscillates between a high and a low state at defined intervals. Typical clock signals oscillate with a 50% duty cycle. However, clocks having other duty cycles are also commonly employed. Circuits using clock signals for synchronization become active upon one of the rising or falling edge of the clock signal.
A so-called, “clock multiplexer” refers to a circuit, as typically exists within a linearly expandable router, for selecting at least one clock signal from a plurality of available clock signals. The selected clock signal(s) serve to trigger other elements. When selecting among available clock signals, the output signal selected by the clock multiplexer should not include any undefined pluses. Undefined pulses occur, for example, when a selected clock signal undergoes a disruption. Such a disruption can include a missing clock signal as well as a clock signal that fails to switch states as expected. Some times, an input clock signal will remain “stuck” indefinitely at one logic state or the other. Such disruptions frequently produce undefined pulses including runt pulses, short pulses, pulses of indefinite duration, glitches, spikes and the like.
Prior art attempts to avoid undefined pulses at the output of a clock multiplexer include so-called “safe” clock multiplexers. A typical safe clock multiplexer switches from a presently selected input to a next selected input in an orderly manner. Thus, a safe multiplexer does not switch until the selected input clock signal transitions to a known state and the subsequently selected clock signal transitions to the same state as the previously selected clock signal.
However, prior art safe clock multiplexers have drawbacks. For example, when a presently selected clock signal fails to transition to a known state, a safe clock multiplexer will often lack the ability to switch to another clock signal. Prior art safe clock multiplexers have not tolerated these and other types of clock disruptions.
Thus, a need exists for a technique for providing a selected one of a set of clock signals, such as within a linearly expandable router, that overcomes the aforementioned disadvantages